1. Field of the Invention
The present invention relates to a wiring board having the resin insulating layer, a via penetrating the insulating layer, and a conductor layer formed on the resin insulating layer and via, and a method of producing the wiring board, and specifically to a wiring board in which the via and conductor layer is formed of the plating, and the via is a filled via which is filled with the plating, and a method of producing the wiring board.
2. Description of the Related Art
Conventionally, the wiring board in which a filled via penetrating the approximately plate-shaped resin insulating layer is filled with the plating and formed, and the conductor layer is formed thereon by the plating, is well known. For example, in FIG. 9, a wiring board 101 showing a partially enlarged sectional view of a main surface 102 side is shown. An approximately plate-shaped core board 103 is provided at the center of the wiring board 101. The first resin insulating layer 105 is laminated on both surfaces of the core board 103, and further, the second resin insulating layer 107 is laminated thereon. Further, on the second resin insulating layer 107, a solder resist layer (resin insulating layer) 109 is laminated.
In them, on the core board 103, a plurality of approximately cylindrical throughhole conductors 111 penetrating the core board, are formed at predetermined positions. Further, in the first resin insulating layer 105, a plurality of throughholes 113 for the first via penetrating the insulating layer are formed at the predetermined positions, and in each of the throughholes 113, the first filled via 115 is filled and formed by the plating. In the same manner, in the second resin insulating layer 107, a plurality of through holes 117 for the second via are formed at the predetermined positions, and in each of throughholes 117 for the second via, the second filled via 119 is formed. Further, in the solder resist layer 109, a plurality of openings 121 penetrating the resist layer, are formed at the predetermined positions in order to expose pads respectively.
The first conductor layer 123 of a predetermined pattern of the wiring or pad is formed between the core board 103 and the first resin insulating layer 105, and connected to the throughhole 111 of the core board 103 or the first filled via 115 of the first insulating layer 105. Further, also between the first resin insulating layer 105 and the second resin insulating layer 107, the second conductor layer 125 of a predetermined pattern of the wiring 126 or pad 124 is formed, and is connected to the first filled via 115 of the first resin insulating layer 105 or the second filled via 119 of the second resin insulating layer 107. Further, also between the second resin insulating layer 107 and the solder resist layer 109, the third conductor layer 127 of a predetermined pattern of the wiring or pad 128 is formed, and is connected to the second filled via 119 of the second resin insulating layer 107. Then, a portion of the pad 128 of the third conductor layer 127 is exposed in the opening 121 for the pad of the solder resist layer 109, to mount the electronic parts onto the wiring board 101.
In such the wiring boards, the first filled via 115 of the inside or the surface of the first resin insulating layer 105 and the second conductor layer 125 are formed as follows. That is, initially, by the publicly known method, the throughhole conductor 111 is formed in the core board 103, and the first conductor layer 123 is formed on the core board 103, and further, the board 131 formed thereon the first resin insulating layer 105 having the throughhole 113 for the first via, is prepared (refer to FIG. 10).
Next, the electroless plating is conducted on the board 131, and the electroless plating layer shown by a bold line in the drawing is formed on the surface of the first resin insulating layer 105 and in the throughhole 113 for the first via. Then, the plating resist layer 133 of a predetermined pattern is formed on the electroless plating layer (refer to FIG. 10). After that, by using the plating liquid having the character in which, when the plating is conducted on a portion including the hole, the plating is more grown in the hole than the outside of the hole (hereinafter, in the present specification, the plating liquid having such the characteristic is also called the plating liquid for the filled via), the electrolytic plating is conducted on the board 131. Then, as shown in FIG. 10, the plating is filled in the throughhole 113 for the first via and the first filled via 115 is formed, and the electrolytic plating layer is formed on the first filled via 115 and the electroless plating layer of the first resin insulating layer 105.
In this connection, in the plating liquid for the filled via, in order to promote the plating growth in the hole and to inhibit the plating growth outside the hole, a leveling agent (plating inhibitor) such as N series high polymer is normally included. After, the electrolytic plating, the plating resist layer 133 is removed, and when the electroless plating layer covered by the plating resist layer 133 is removed by the etching, the second conductor layer 125 of the predetermined pattern is formed. In this manner, the first filled via 115 and the second conductor layer 125 are formed on the first resin insulating layer 105.
After that, on the first resin insulating layer 105 and the second conductor layer 125, the second resin insulating layer 107 is laminated, and in the same manner as described above, the second filled via 119 and the third conductor layer 127 are newly formed. Then, on the second resin insulating layer 107 and the third conductor layer 127, when the solder resist layer 109 having the opening 121 for the pad is formed, the wiring board 101 shown in FIG. 9 is produced.
However, when, by using the plating liquid for the filled via, the first filled via 115 and the second conductor layer 125 are formed, because the condition of the second conductor layer 125 is different depending on the position in the board 131, the disadvantage occurs. This is considered that it is influenced from the reason that, at the time of the electrolytic plating, the current density is biased in the board 131.
Relating to this disadvantage, when the description is specifically conducted on the board 131 shown in FIG. 10, in a portion in which the arrangement of the formed wiring 126 or pad 124 is coarse, that is, in a portion in which the pattern of the plating resist layer 133 is coarse, (a left side portion in the drawing), the current density becomes high at the time of the electrolytic planing, and the leveling agent in the plating liquid is easily attracted in this portion. When the vicinity of the first filled via 115L existing in the left side portion in FIG. 10 and a pad 124L of the second conductor layer 125 is observed, as a partially enlarged sectional view is shown in FIG. 11, the growth of the plating particle is inhibited in the pad 124L, as the result, the thickness of the plating layer (the thickness of the pad 124L, that is, the second conductor layer 125) becomes also comparatively thin. Further, as the result that the growth of the plating particle is inhibited, there is a case where an area in which the plating particle with extremely small particle diameter partly exists, is generated. In contrast to this, in a portion in which the arrangement of the wiring 126 or the pad 126 is dense, that is, in a portion in which the pattern of the plating resist layer 133 is dense, (a right side portion in the drawing), the current density at the time of the electrolytic plating is lowered, and the leveling agent in the plating solution is hardly attracted. Therefore, when the vicinity of the wiring 126R of the second conductor layer 125 existing in the right side portion in FIG. 10 is observed, as the partially enlarged sectional view is shown in FIG. 12, the plating particle grows comparatively large and the thickness of the plating layer (the wiring 126R, that is, the thickness of the second conductor layer 125) becomes comparatively thick.
Further, when only the pad 124 or the wiring 126 is observed, because the plating resist layer 133 has the characteristic by which the leveling agent is hardly attracted, as shown in FIG. 11 and FIG. 12, in its vicinity, the leveling agent is hardly collected, the plating particle grows comparatively large, and the thickness of the plating layer also becomes comparatively thick. On the one hand, because a portion apart from the plating resist layer 133 (central portion) easily attracts the leveling agent, the growth of the plating layer is inhibited, and the thickness of the plating layer also becomes comparatively thin. As the result, in the pad 124L shown in FIG. 11, the peripheral portion becomes the shape in which the portion is leaped up from the central portion. Further, also in the wiring 126R shown in FIG. 12, its both edge portions become the shape in which the portions are leaped up from the central portion.
Further, in the board 131, in the vicinity (not shown) of the connection point to the electrode of the electrolytic plating, because the current density becomes relatively high, and the leveling agent is easily attracted, the growth of the plating particle is inhibited, and the thickness the of plating layer also becomes comparatively thin, however, at the portion apart from the connection point of the electrode, because the current density becomes low, and the leveling agent is hardly attracted, the plating particle is grown, and the thickness of the plating layer also becomes comparatively thick.
As described above, because the conductor layer (the second conductor layer 125) becomes thick and thin depending on the position, or becomes the shape in which it is leaped up at the peripheral portion of the pad 124 or at both edge portions of the wiring 126, the conductor layer has a poor appearance. In the same manner, this can be said also for the third conductor layer 127.
Further, before the second resin insulating layer 107 is laminated on the second conductor layer 125, or before the solder resist layer 109 is laminated on the third conductor layer 127, when the surface of the second conductor layer 125 or the third conductor layer 127 is subjected to surface roughening by etching, the roughening unevenness is generated due to the non-uniformity of the distribution of the plating particle of the surfaces of the first and the second conductor layers 125 and 127, and the poor appearance is generated. Further, in a portion in which minute plating particles of, for example, 0.1 xcexcm are collected, the fine roughened surface is not formed, and there is case where the close contact intensity of the second conductor layer 125 with the second resin insulating layer 107, or the close contact intensity of the third conductor layer 127 with the solder resist layer 109 is lowered.
Further, for example, in the peripheral portion which is leaped up convex-shaped in the second conductor layer 125 surrounded by the dashed line in FIG. 9, the insulation space to the third conductor layer 127 formed on the second resin insulating layer 107 through the layer 107, is reduced, and there is also a case where the electric fault such as the short circuit occurs between the upper and lower conductor layers.
In view of such the actual condition, the present invention is attained, and an object is to provide a wiring board and a method of producing the wiring board, in which, in the wiring board having a resin insulating layer, filled via which penetrates the insulating layer and which is filled and formed by the plating, and the conductor layer formed by the plating on them, the thickness of the conductor layer is substantially uniform.
The means for solving the problems is a wiring board which comprises: a resin insulating layer; a filled via which is filled and formed by the plating in the throughhole penetrating the resin insulating layer; and a conductor layer formed by the plating on the resin insulating layer and the filled via, wherein the conductor layer is provided with an electroless plating layer formed on the resin insulating layer and filled via, and an electrolytic plating layer formed on the electroless plating layer, and the particle size distribution of the plating particle is substantially uniform without depending on the position.
As described above, in the wiring board in which the filled via is filled and formed by the plating, because the plating growth is different depending on the position, the variation is easily caused in the thickness of the conductor layer. However, in the present invention, the conductor layer has a very thin electroless plating layer which is formed on the resin insulating layer and the filled via, and the electrolytic plating layer which is formed on the electroless plating layer and in which the particle size distribution of the plating particle is substantially uniform. This electrolytic plating layer can be said, because the particle size distribution is substantially uniform without depending on the position, that it is grown at substantially the same speed without depending on the position, and the thickness is substantially the same without depending on the position. Accordingly, also as the whole conductor layer including the electroless plating layer, the thickness is substantially uniform, and the appearance is good.
In the present application, the particle size distribution was observed with SEM or FE-SEM. The particle size was observed by cross sectional SEM photographs.
Further, in the above wiring board, the conductor layer surface is made a surface roughened by etching, and it is better when a wiring board has the upper resin insulating layer on the conductor layer and the resin insulating layer.
In the case where the particle size distribution of the plating particle (the plating particle of the electrolytic plating layer) is substantially uniform, when the conductor layer surface is made rough surface by the etching, the conductor layer surface is uniformly made rough surface without unevenness. Accordingly, in the wiring board of the present invention, because the conductor layer surface is made substantially uniform roughened surface, there is no uneveness in the close contact strength between the conductor layer and the upper resin insulating layer formed thereon.
In this case, the particle size of the plating of the electrolytic plating layer is preferable when it is not smaller than about 1 xcexcm. It is for the reason that, because there is no uneveness in the close contact strength between the conductor layer and the upper resin insulating layer (there is no uneven portion in which the plating particle of particle size of not larger than 0.1 xcexcm is unevenly distributed), and the surface roughness of the roughened surface can be increased, these close contact strength can also be increased.
Further, other resolving means is the wiring board having the resin insulating layer and the filled via filled and formed in the throughhole penetrating the resin insulating layer by the plating, and the conductor layer which is formed by the plating on the resin insulating layer and the filled via, and the conductor layer is the wiring board having the electroless plating layer formed on the resin insulating layer and the filled via, and the electrolytic plating layer of substantially uniform thickness formed on the electroless plating layer.
In the wiring board in which the filled via is filled and formed by the plating, because the plating growth is different depending on the position, the variation is easily generated in the thickness of the conductor layer. However, in the present invention, the conductor layer is composed of the very thin electroless plating layer formed on the resin insulating layer and filled via, and the electrolytic plating layer with substantially uniform thickness formed on the electroless plating layer. Accordingly, as the whole conductor layer, the thickness is substantially uniform and the appearance is good.
Further, in the above wiring board, in the electrolytic plating layer, the particle size distribution of the plating particle is substantially uniform without depending on the position, and the conductor layer surface is a surface roughened by etching, and it is better that the wiring board has the upper resin insulating layer provided on the conductor layer and the resin insulating layer.
In the case where the particle size distribution of the plating particle (plating particle of the electrolytic plating layer) in the vicinity of the conductive layer surface is substantially uniform, when the conductor layer surface is roughened by etching, the conductor layer surface is roughened uniformly without unevenness. Accordingly, in the wiring board of the present invention, because the conductor layer surface is made roughened surface with uniform roughness, there is no uneveness in the close contact strength between the conductor layer and the upper resin insulating layer formed on the conductor layer.
In this case, it is preferable that the particle diameter of the electrolytic plating layer is not smaller than about 1 xcexcm. this is because there is no uneveness in the close contact strength between the conductor layer and the upper resin insulating layer (there is no non-uniform portion in which the plating particle of the particle diameter of not larger than 0.1 xcexcm is unevenly distributed), and the surface roughness of the roughened surface can be increased, therefore, the close contact strength can also be increased.
Further, it is better when the wiring board is the wiring board described in any one of the above, and it is the wiring board having the upper conductor layer on the upper resin insulating layer.
As described above, on the conductor layer, there is no spring-up on the peripheral portion of the pad or both edge portions of the wiring, and the thickness is substantially uniform. Accordingly, the insulation distance between the conductor layer and the upper conductor layer formed through the upper resin insulating layer ca be sufficiently kept, and the electric failure such as the short circuit or lowering of the insulation resistance is hardly generated.
Further, another resolution means is as follows: a method of producing the wiring board having the filled via filled and formed in the throughhole penetrating the resin insulating layer, and the conductor layer formed by the plating on the resin insulating layer and the filled via, wherein the method of producing the wiring board has: in the board having the first electroless plating layer formed in the throughhole and on the resin insulating layer, the first electrolytic plating process by which the electrolytic plating is conducted on the first electroless plating layer by the first plating liquid by which, when the plating is conducted on a portion including the hole, the plating is further grown in the hole than the outside of the hole, and the inside of the throughhole is filled with the plating and the filled via is formed, and on the substantially whole surface of the first electroless plating layer of the filled via and resin insulating layer, the first electrolytic plating layer is formed; and the plating layer remove process by which the first electroless plating layer on the first electrolytic plating layer and the resin insulating layer is removed. An example of the first electrolytic plating liquid includes Cu-Brite VF by EBARA-UDYLITE CO., LTD.
In the present invention, initially, on the electroless plating layer of the board, the filled via and the first electrolytic plating layer are formed by the first plating liquid by which the plating is further grown inside the hole than outside the hole (the first electrolytic plating process). The first plating liquid makes the growth of the plating different depending on the position, thereby, because the inside of the throughhole can be effectively filled by the plating, it is convenient for forming the filled via. Further, in this process, different from the conventional process, because the plating resist layer is not formed on the board, there is no variation of the thickness in the conductor layer, such as the difference in the thickness depending on the position or spring-up.
After the first electrolytic plating process, the first electrolytic plating layer formed on substantially whole surface and the first electroless plating layer below it (the electroless plating layer on the resin insulating layer) are removed by, for example, etching or mechanical grinding (the plating layer removal process).
In the board after the plating layer removal, because the throughhole in the resin insulating layer is filled by the plating, the surface of the resin insulating layer and the upper surface of the filled via are substantially on the same surface. That is, the surface of the board is substantially flat. On such the substantially flat board surface, the uniform thickness conductor layer can be easily formed.
Accordingly, according to the present invention, even when the filled via exists, the wiring board in which the thickness of the conductor layer is substantially uniform can be easily produced.
Further, in the method of producing the wiring board, it is better in the plating layer removal process when a resin roughening process by which, by the mechanical grinding, the first electrolytic plating layer and the first electroless plating layer on the resin insulating layer are removed, and the surface of the resin insulating layer from which the plating layer is removed, is etched and roughened, is provided.
To etch and rough the surface of the resin insulating layer is for the reason to increase the close contact strength between the resin insulating layer and the conductor layer formed thereon, and further when the resin insulating layer is laminated on the upper portion, it is for the reason to increase the close contact strength between the resin insulating layer and the upper resin insulating layer.
Conventionally, this resin roughening process is conducted after the resin insulating layer is formed, and before the electroless plating layer is formed. However, in the plating layer removal process, when the plating layer is removed by the mechanical grinding, not only the plating layer, but also the resin insulating layer below it is ground, thereby the surface roughness is sometimes reduced.
In contrast to it, in the present invention, because the resin roughening process is conducted after the plating layer removal process, the conductor layer can be formed thereon under the condition that the surface of the resin insulating layer is formed to the desired surface roughness, and further, the upper resin insulating layer can also be formed. Accordingly, the reliability of the close contact strength between: the resin insulating layer; and the conductor layer or the upper resin insulating layer can be increased.
Further, in the method of producing the wiring board described in any one of the above description, the method of producing the wiring board is better when it has: the electroless plating process to form the second electroless plating layer on substantially whole surface on the filled via and on the resin insulating layer, from which the plating layer is removed; and the second electrolytic plating process by which, in the second electroless plating layer, on a portion exposed to the outside, the electrolytic plating is conducted by the second plating liquid by which the plating is at least the same degree in the outside of the hole as in the inside of the hole, and the second electrolytic plating layer is formed.
An example of the second electrolytic plating liquid includes Curex-S by Electroplating Engineers of Japan Ltd.
In the present invention, after the plating layer removal process, or after the resin roughening process when there exists the resin roughening process, the second electroless plating layer is formed on the board surface (on the filled via and on the resin insulating layer). Next, for example, the plating resist layer of a predetermined pattern is formed on the electroless plating layer, and the electrolytic plating is conducted by the second plating liquid which has, when the plating is conducted on a portion including the hole, the characteristic by which the plating is grown to the same degree or more in the outside of the hole than in the inside the hole, on the second electroless plating layer exposed to the outside from the plating resist layer (the second electrolytic plating process). In that case, in the second plating liquid, because the plating grows substantially uniformly, the second electrolytic plating layer with substantially uniform thickness can be formed.
After that, the plating resist layer is removed, and when the second electroless plating layer covering the plating resist layer is etched and removed, the predetermined patterned conductor layer can be formed. Because this conductor layer is composed of the very thin second electroless plating layer, and the second electrolytic plating layer with substantially uniform thickness, its thickness is substantially uniform and the appearance is good.
Alternatively, after the second electroless plating layer formation, in succession, on substantially whole surface of the electroless plating layer which is exposed to the outside, the electrolytic plating by the second plating liquid may be conducted (the second electrolytic plating process). In this case also, when the second plating liquid is used, the second electrolytic plating layer with substantially uniform thickness can be formed.
After that, when a predetermined patterned etching resist layer is formed on the second electrolytic plating layer, and the second electrolytic plating layer exposed from this etching resist layer and the second electroless plating layer below it, are removed by etching, the predetermined patterned conductor layer can be formed. Because also the conductor layer produced as described above is composed of the very thin second electroless plating layer and substantially uniform second electrolytic plating layer, its thickness is substantially uniform and the appearance is good.
As described above, according to the present invention, even when the filled via exist, the conductor layer whose thickness is substantially uniform and whose appearance is good, can be formed.
Further, in the method of producing the wiring board, it is better when the method of producing the wiring board has: after the second electrolytic plating process, the roughening process to etch and roughen the conductor surface; and the upper resin layer forming process to form the upper resin insulating layer on the roughened conductor layer and the resin insulating layer.
Because the plating particle near the surface of the conductor layer before the roughening process (the plating particle of the second electrolytic plating layer) grows substantially uniformly, that is, it has substantially uniform largeness, when the surface of the conductor layer is etched and roughened in the roughening process, the surface has the roughened surface with the substantially uniform roughness. Accordingly, when the upper resin insulating layer is formed in the upper insulating layer formation process, there is no uneveness in the close contact strength between the roughened conductor layer and the upper resin insulating layer.
Further, in the method of producing the wiring board, it is better when it forms the second electrolytic plating layer formed of the plating particle larger than the particle diameter of about 1 xcexcm in the second electrolytic plating process. The preferable upper limit of the plating particle diameter in the second electrolytic plating process is 3 xcexcm.
When the plating particle of the second electrolytic plating layer in the vicinity of the surface of the conductor layer is very small, the roughened surface having the desired roughness can not be obtained in the roughening process, and the close contact strength between the conductor layer and the upper resin insulating layer is sometimes lowered.
In contrast to this, in the present invention, because the particle diameter of the plating particle of the second electrolytic plating layer forming the vicinity of the surface of the conductor is large, that is, lager than about 1 xcexcm, the roughened surface with the desired roughness can be formed in the roughening process. Accordingly, the close contact strength between the conductor layer and the upper resin insulating layer can be increased.
Further, in the method of producing the wiring board described in any one of the above description, it is better when the method of producing the wiring board has the upper conductor layer forming process to form the upper conductor layer on the upper resin insulating layer.
As described above, the conductor layer does not have any variation in the thickness, and can have substantially uniform thickness. Accordingly, even when the upper insulating layer is formed thereon, and further the upper conductor layer is formed on them, there is no portion in which the insulation distance is reduced, between the conductor layer and the upper conductor layer formed through the upper resin insulating layer. Accordingly, the electric failure such as the short circuit between upper and lower conductor layers or the lowering of the insulation resistance is hardly generated.